Shy of Retiring

     It is common for DSP systems to be designed a bit poorlly in terms of the balance between ADC accuracy and clock accuracy. I think this is becaue many designers do not realise that the two are linked: error in the clock timing leads to errors in the sampled signal. The diagram shows an analogue signal which is held on the rising edge of a clock signal. If the clock edge occurs at a different time than expected, the signal will be held at the wrong value. In the diagram, the signal is rising and so the held value is higher than it should be. Errors introduced by timing jitter are as important as those caused by quantization, but are often forgotten. It is sadly common to see DSP systems where a lot of care has gone into the analog design and the selection of analog-to-digital converters with high precision and accuracy, but where the design is let down by a poor quality clock. A good design would balance the choice of clock accuracy against the ADC, and t...

     I am struck by how the term 'sample-and-hold' puts the two operations back-to-front. There are two steps to the conversion of an analog signal to digital form. The two are often confused, and the term "analog-to-digital conversion" is often (mistakenly) used to refer to both steps in the process. This confusion can hide important engineering choices. The idea of analog-to-digital conversion is to take a continually varying analog signal and convert that to a discrete set of samples taken (usually) at some regular time interval. The conversion is in fact a form of measurement, and for each sample will produce just one measured value. The problem here is, that the signal is continuously varying and so the (single) measurement will be some kind of average of the variation. Worse, the process of conversion to digital form can take some time and be done in stages - for example the method of "successive approximation" makes a first guess at the value, which...